Synthèse d'architectures de circuits FPGA tolérants aux défauts. (Defect tolerant fpga architecture synthesis)

The increasing integration density according to Moore's law is being slowed due to economic and physical limits. However, this technological evolution involves an higher number of physical defects after manufacturing circuit. As yield goes down, one of the future challenges is to nd a way to use a maximum of fabricated circuits while tolerating physical defects spread all over the chip. Fiel Programmable Gate Array (FPGA) are integrated circuits that contain logic blocks and recon gurable interconnect. Their ability to integrate more complex applications, their exibility and good performance make FPGAs the perfect target architecture. The aim of this thesis is to propose an FPGA architecture containing mechanisms to tolerate more than 20% of defective resources after manufacture. The rst part of the manuscript studies the di erent FPGA architectures (mesh and tree), their advantages and disadvantages and di erent defects bypass techniques. These techniques can be classi ed into two categories : software and hardware redundancy techniques. In view of their performance, we used hardware redundancy techniques. In addition, these techniques can be easily adapted to our FPGA architecture. In the second part of this thesis, we present the target architecture called Mesh of Clusters (MoC). This architecture combines the advantages of mesh architectures (genericity) and tree (reduction of the interconnect). The results shows that with MoC architecture the utilization of the interconnect is reduced by 40% compared to mesh architecture. The third contribution of this thesis is the development of a method to identify the most critical blocks in the FPGA and the impact of all bypass techniques on the architecture and on the criticality. Finally, we de ne the performance of all bypass techniques in terms of defect tolerance, timing and area overhead. The best results shows that around 25% defects can be bypassed bypassed for an area overhead of 30% and timing overhead of 10%. However, these techniques have a signi cant impact on the FPGA area, that's why we propose local redundancy techniques applying redundancy techniques only on the most critical blocks of the FPGA. These techniques can tolerate a large number of defects with a minimal impact on the surface and on the timing (For the best case, 40% defects can be bypassed for an area overhead of 20% and timing overhead of 10%). Finally, thanks to these local redundancy techniques, we are able to tolerate more than 20% of defect on the FPGA architecture. In addition, the designer can x his own metric in terms of area, timing and defect tolerance.